This invention relates generally to integrated circuit design and, in particular, to debugging a programmable logic device.
In the field of electronics, various electronic design automation (EDA) tools are useful for automating the process by which integrated circuits, multi-chip modules, boards, etc., are designed and manufactured. In particular, electronic design automation tools are useful in the design of standard integrated circuits, custom integrated circuits (e.g., ASICs), and in the design of custom configurations for programmable integrated circuits. Integrated circuits that may be programmable by a customer to produce a custom design for that customer include programmable logic devices (PLDs). As used herein programmable logic devices refer to any integrated circuit that may be programmed to perform a desired function and include programmable logic arrays (PLAs), programmable array logic (PAL), field programmable gate arrays (FPGA), complex programmable logic devices (CPLDs), and a wide variety of other logic and memory devices that may be programmed. Often, such PLDs are designed and programmed by a design engineer using an electronic design automation tool that takes the form of a software package.
In the course of generating a design for a PLD, programming the PLD and checking its functionality on the circuit board or in the system for which it is intended, it is important to be able to debug the PLD because a design is not always perfect the first time. Before a PLD is actually programmed with an electronic design, a simulation and/or timing analysis may be used to debug the electronic design.
Once the PLD is actually programmed with the electronic design after initial debugging, a customer or potential user may wish to evaluate the PLD. At this point, the customer/potential user may want to modify the boot memory contents. The program update of the boot memory is time consuming because a hardware compilation is required since the boot memory is in a read-only state. That is, the program contained in on-chip memory requires changing software, compiling that software and then compiling the design to update the configuration. Thus, a software design engineer may wait for up to an hour when making minor modifications, which hampers progress in fixing a program or a design.
As a result, there is a need to solve the problems of the prior art to more efficiently enable the modification of a boot memory contained within a PLD.